Smart Embedded Vision

Overview

As compute workloads move to the edge, PolarFire FPGAs offer 30-50% lower total power than competing mid-range FPGAs, with 5-10x lower static power, making them ideal for a new range of compute-intensive edge devices, including those deployed in thermally and power-constrained environments. PolarFire FPGA Smart Embedded Vision solutions include video, imaging, and machine learning IP and tools for accelerating designs that require high performance in low-power, small form-factors across the industrial, medical, broadcast, automotive, aerospace and defense markets.

Key PolarFire Benefits in Smart Embedded Vision

1.竞争中密度FPGA的最低总功耗

• 竞争中密度FPGA的功耗降低30％至50％
• Extended battery life in portable devices like drones, AR/ VR headset, HUDs, portable Ultrasound etc.
• Reduce system cost by eliminating thermal fans and heat sinks
• Realize lower power in 4kp60 HDMI 2.0, 12G SDI, 10G Ethernet, 12.5G CoaXPress etc. using SERDES lanes rated for 90 mW at 10G

2。Small form-factor packages starting at 11x11 mm for 100K LE

• Create compact modules with 100K (11x11 mm) and 200K (11x14.5 mm) LE devices
• Design your next-gen vision platform with small form-factor PolarFire FPGAs with unmatched features like DDR4, LPDDR3, 12.7G SERDES, 1.6 Gbps LVDS I/Os and PCIe Gen2x4

Power Consumption Competitive Benchmark with 16 Channel Audio-Video Bridge Design Example
该example design demonstrates an Audio-to-Video bridge implementation. It uses 56% LUTs, 35% Mathblocks, DDR3 and 16 channel transceivers in a PolarFire MPF500T device. Benchmarks demonstrate up to 52% lower power consumption when compared to similar density FPGAs.

16.Channel AVB Switcher Power Estimator Results

AVB Switcher (4 Ch.)	静态（W）	Core Dynamic (W)	I/O* (W)	Transceiver* (W)	总权力（W）
Polar Fire (MPF500TS)	1.4.9.3.	2.474	2。9.9.1	0.769	7.。7.27.
极火（MPF500TLS **）	1.059	2.474	2。9.9.1	0.769	7.。29.3.
Kintex 7 (XC7k325T-2)	1.796	5.。4.7.1	3.。9.7.1	4.079	15.317
Arria V(5AGXFB3H)	2.572	4.。3.5.0	5.。4.5.1	1.651	14.。025
Zynq US+(XCZU7EV-1L(0.72v))	2。8.6.4.	2.165	4.。011	2.694	11。7.

* I / O和收发器功率估计包括静态和动态组件。**功率优化设备

16.Channel AVB Switcher Resource Utilization

Resources	Count	接口	Lanes	I/Os	率
4.LUT	27.1K	收发器	16.	-	2。9.7.Gb/s
达夫	188 k
LSRAM.	816.
uSRAM	24.9.	3x72位DDR3.	-	3.5.1	8.00 Mb/s
mathblock.	500.

Learn More

Learn why Microchip FPGAs consume up to 50% lower-power than competitive mid-density FPGAs?	Learn More
Did you know that PolarFire is the world's best FPGA at protecting your IP?	Learn More
Do you know what makes Microchip FPGAs the most reliable in the Industry?	Learn More
了解Libero，IDE用于偏光。	Learn More
了解PolarFire如何满足您的下一代视觉平台要求。	Learn More

入门

PolarFire Video FMC Portfolio

＃	Description	Links
1	Explore and Purchase the PolarFire Video Kit.	套件网页
2	Explore and Purchase the CoaXPress FMC Daughter Card.	FMC网页
3.	Explore and Purchase the SDI FMC Daughter Card.	FMC网页
4.	探索并购买USXGMII FMC子卡。	FMC网页
5.	Download Libero SoC v12.1 Software for PolarFire FPGAs.	Libero SoC v12.1 Download
6.	该套件与一年的免费利比罗SoC金牌许可证。注册您的软件ID。	Licensing
7.	下载双摄像头视频套件演示指南。	DG0849
8.	Download Design File, Programming Files and GUI Installer.	设计文件那Program Files那GUI安装程序
9.	Explore the Imaging and Video IPs tab for more information.	转到成像和视频IPS选项卡。
10	Explore Low-Power PolarFire designs. Download the Power Estimator UG and Excel Tool.	Low Power UG那Power Estimator

出于Box演示设计的怪异视频套件

Demo Guide & Programming Files

DG0849: PolarFire 4K FPGA Dual Camera Video Kit Demo Guide 设计文件s(ZIP, 584 MB) Simulation Files(ZIP,173 MB) Programming Files(ZIP, 11.6 MB) GUI安装程序(ZIP, 223MB)

05/2020

成像和视频IPS

Microchip的FPGA产品组合通过内部开发和使用我们的第三方合作伙伴生态系统提供可扩展的生产准备IP。我们的内部IP投资组合涵盖了MIPI，SLVS-EC，Coaxpress，串行数字接口（SDI），HDMI等的最新嵌入式Vision IP，而我们的合作伙伴学习，H.264，Dyabo8855下载isplayPort和HDCP IP，持续增加了更多的IPS。

Click hereto see our Partner IPs.

内部DirectCore智能嵌入式Vision IPS for PolarFire FPGA

IP.	Features	文件
MIPI CSI-2 Rx	Up to 1.5 Gbps per lane x 4 lanes, 4Kp60	UG0806: MIPI CSI-2 Rx UG
MIPI CSI-2 Tx	Up to 1 Gbps per lane x 4 lanes, 4Kp30	UG0826：PolarFire MIPI CSI-2 TX UG
HDMI 2.0 Rx	Supports HDMI 2.0, 8-bit color, 1080p60	UG0863：HDMI RX IP UG
HDMI 2.0 Tx	支持HDMI 2.0和1.4,4KP60	UG0862: HDMI TX IP UG
USXGMII	Supports 1, 2.5, 5 and 10G over Ethernet Cu PHY: EDCS-1150953	Request Information
3.G/HD SDI Rx	1.4.8.5.Gbps HD-SDI and 2.97 Gbps 3G-SDI	CoreSDIRX v2.2 Hand Book
3.G/HD SDI Tx	1.4.8.5.Gbps HD-SDI and 2.97 Gbps 3G-SDI	CoreSDITX v2.2 Hand Book
6.G/12G SDI Rx	6 Gbps (1080 p120, 2160 e)和12 Gbps (2160 p60)	CoreUHD_SDIRX v2.0 Hand Book
6.G/12G SDI Tx	6.Gbps (1080p120, 2160p30) and 12 Gbps (2160p60)	coreuhd_sditx v2.0手册
SLVS-EC	Supports 2.3 Gbps per lane x 2 lanes in RAW8 data type	UG0877: SLVS-EC Rx UG
CoaXPress v1.1	6.25 Gbps下来，20.83 Mbps Up连接，主机和设备IP	UG0875：Coaxpyabo8855下载ress IP UG
ISP捆绑包	Bayer, Video DMA, Alpha Blending, Color Space (RGB, YCbCr), Image Sharpening, Display Enhancement, Edge Detection, Display Controller, Pattern Generation, MIPI CSI-2 Rx/ Tx and LVDS 7:1 Display Rx/ Tx	UG0640：拜耳插值UG UG0693：边缘检测UG UG0639: Color Space Conversion UG UG0641: Alpha Blending UG UG0646: Display Enhancement UG UG0651: Scaler UG UG0682：模式发生器UG UG0649: Display Controller UG

For evaluation/purchase of any of the IPs, please fill in the请求信息形式或联系本地销售额in your area.

CompanionCore Smart Embedded Vision Partner IPS

Partners	Description	Supported FPGAs
	HDMI 2.0B / 1.4，DisplayPort 1.4a HDCP 1.x/ 2.x	PolarFire FPGAs
	同轴12yabo8855下载.5Gbps主机和设备 交钥匙解决方案	PolarFire FPGAs
	H.264 Encoder JPEG 2000 Compression	PolarFire FPGAs
	DDR4/3, LPDDR4 CSI-2, DSI-2	PolarFire FPGAs SmartFusion2 SoC FPGAs IGLOO2 fpga
	Core Deep Learning (CDL) Caffe CNN Compiler	PolarFire FPGAs
	Alpha Blender, Chroma Resample, Image Rotation SD，SDIO和MMC控制器	SmartFusion2 SoC FPGAs IGLOO2 fpga
	H.264 Encoder	SmartFusion2 SoC FPGAs IGLOO2 fpga
	USB 3.1 Gen1 Device (5Gbps) USB 3.1 Gen2 Device (10Gbps)	PolarFire FPGAs

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vectorblox ai.

Overview

Development Flow

文件

入门

Deployment Options

VectorBlox Accelerator软件开发套件

该VectorBlox Accelerator SDK contains different tools that compile a neural network description from TensorFlow and ONNX into a Binary Large Object (BLOB) that is stored in flash and loaded into the DDR memory during execution. 模型优化-converts a trained network to a common intermediate representation (IR) from various training frameworks (TensorFlow, PyTorch etc.) and cleans the network for inference. Several components used during training, that slow down calculations, e.g. batching operators and fuse layers are removed at this step. Quantization-converts optimized networks from 32-bit floating point precision (FP32) to INT8 representation. Quantization enables networks to be represented using less memory with minimal loss in accuracy. Calibration-involves adjusting activations and weights of a model represented in INT8 precision. Runtime Generation-creates a Binary Large Object (BLOB), that is written into the SPI flash of the hardware development platform and is loaded into the DDR memory during runtime

CoreVectorBlox IP

该CoreVectorBlox IP consists of a Matrix processor (MXP) and a MXP CNN IP. It can be instantiated as a single core accelerator or in multi-cores when neural network workloads need to be shared. The MXP consists of eight 32-bit ALUs and is responsible for elementwise tensor operations like add, sub, xor, shift, mul, dotprod etc. The MXP CNN IP consists of a 2D array of multiply and accumulate functions implemented using math blocks. As the name suggests, the MXP CNN IP is responsible for executing the convolutional layers of CNNs. Multiple networks can be overlayed during the runtime and switched dynamically. It is also possible to run simultaneous networks on a single CoreVectorBlox instantiation through time-slicing.

Development Flow

Step 1: Prepare your trained model

使用SDK中提供的Python脚本将培训的模型转换为称为二进制大对象（BLOB）的优化INT8表示。通过VectorBlox模拟器运行BLOB以验证网络的准确性，并确保成功转换网络。

Step 2: Prepare your hardware

该PolarFire Video Kitis configured to run as an AI enabled Smart Camera. The SDK includes a pre-compiled kit image bitstream. Write the bistream into the PolarFire FPGA using theFlashPro.programmer included with the kit. Write the BLOB, generated from Step 1, into the SPI flash of the kit.

Step 3: Write your embedded code

Use the provided embedded code in C/C++ basedSoftConsoleIDE and generate and program the hex file. Connect the video kit to a HDMI monitor and turn it on. Modify the embedded code to load and run many CNN BLOBs, switch CNNs dynamically on the fly or load CNNs sequentially for simultaneous inferencing.

文件

Document	Description
CoreVectorBlox IP手册	CoreVectorBlox Libero IP数据表
VectorBlox Programmers Guide	VectorBlox SDK安装和工具流环境指南
VectorBlox Demo Guide	入门Guide for VectorBlox in the PolarFire Video Kit
Core VectorBlox IP Release Notes	Release Notes for current CoreVectorBlox IP version

入门

Steps

Step 1: Download the VectorBlox SDK from Github and use the Programmers Guide to install

Step 2: Purchase the PolarFire Video Kit

Step 3: Download and Install Libero 12.5 SP1

Step 4: Get a free Libero Silver License

Step 5: Get a free Libero VectorBlox License, required in addition to Step 4

Step 6: Download the Libero 12.5 Smart Camera Reference Design for the PolarFire Video Kit

第7步：阅读程序员指南andDemo Guide to install the Reference Design

Deployment Options

PolarFire Video Kit
Smart Camera Reference Design using the PolarFire Video Kit
1.视频帧跟从ed via MIPI CSI-2 2。And stored in the DDR via AXI-4 interconnect 3.。Before inference – the frame is read back from the DDR 4.。Converted from RAW to RGB, RGB to planer R, G, B and written back into DDR 5.。CoreVectorBlox engine runs inference on R, G, B arrays and writes results back into DDR 6.。Mi-V sorts probabilities, creates an overlay frame with bounding boxes, classification results, fps etc. and stores the frame in DDR 7.。该original video frame is read and blended with the overlay frame and sent out to an HDMI display

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